Self-aligned phosphorus doped polysilicon gate MOS device radiation hardening

The radiation behavior of the drain and the source regions of self-aligned gate MOSFETs was investigated with respect to the ion implantation energy, the dose, and the thickness of the masking polysilicon gate electrode. The test specimens included MOS capacitors, n- and p-channel SOS transistors, and 8-bit arithmetic logic unit CMOS/SOS circuits for spaceborne computers. Device fabrication is described, together with the radiation exposures, which ranged from 50,000 rads/hr to 2,100,00 rads/hr in steps. An optimum radiation-hardened production process for the MOSFETs was found to depend on the gate oxide growth conditions, the gate oxide thickness, the deposition of the gate electrode, the high temperature cycles after growth of the gate oxide layer, the n+ and p+ source drain implantation energy and dose, and the masking polysilicon gate electrode thickness. Increasing the polysilicon gate thickness from 5000 A to 5500 A decreased the sift in the n-channel threshold from -6.1 V to -1.8 V at 300,000 rads total dose. The phosphorus implantation energy was also decreased from 150 keV to 125 keV. The major device radiation degradation mechanism was identified as the gate oxide damage caused by heavy n+ and p+ ion implantation processes.