Nanosecond NMOS VLSI current mode logic
Abstract
Current mode logic (CML) is used to obtain NMOS VLSI logic gates with nanosecond delays at a speed power product of 1.5 pJ. The gates use a reference voltage generated by the difference between an enhancement- and a depletion-type MOSFET. A depletion-type MOSFET is used for the current sources and the loads. The gates have been designed with a logic swing of 2 V in a 2.5-micrometer NMOS VLSI technology, simulated, and their circuit performance is studied.
- Publication:
-
IEEE Transactions on Electron Devices
- Pub Date:
- April 1982
- DOI:
- Bibcode:
- 1982ITED...29..781E
- Keywords:
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- Field Effect Transistors;
- Gates (Circuits);
- Logic Circuits;
- Metal Oxide Semiconductors;
- Very Large Scale Integration;
- Depletion;
- Pulse Duration;
- Systems Simulation;
- Time Lag;
- Voltage Generators;
- Electronics and Electrical Engineering