Characterization of CMOS devices for VLSI

CMOS bulk and SOS technologies are discussed for VLSI with emphasis on static and dynamic characteristics of two-input NAND devices. Optimum performance, as measured by propagation delay t(pd) and power dissipation P(d), is obtained for a CMOS/SOS two-input NAND gate with an electrical channel length of 0.75 micron, channel width 5.0 microns, and oxide thickness 450 A with supply voltage of 3.0 V to yield t(pd) of 400 ps and of 250 microwatts at room temperature. Bulk technology performs within a factor of 2 of SOS for t(pd) and P(d). CMOS technologies offer subnanosecond t(pd), similar to ECL bipolar, at the low submilliwatt power levels of CMOS. An analytical expression for t(pd) describes the performance of two-input NAND gates in terms of device modeling and fabrication parameters. Such an expression provides a hierarchical modeling approach to characterize minicells for VLSI.