Composite TiSi2/n+ poly-Si low-resistivity gate electrode and interconnect for VLSI device technology

This paper presents fine-line patterning techniques and device characteristics of MOSFETs with a TiSi2 polycide gate. A coevaporated TiSi2 polycide gate was chosen for this study because it had 2 to 5 times lower resistivity as compared to other silicides. Polycide formation by electron-beam coevaporation is chosen in preference to sputtered TiSi2 because of lower oxygen contamination. The coevaporation technique to form TiSi2 polycide with a sheet resistivity of 1 Omega/square is described. Anisotropic etching of nominally 1-micron lines with a 15:1 etch selectivity against oxide is reported. Measurements of metal-semiconductor work function, fixed oxide charge density, dielectric strength, oxide defect density, mobile-ion contamination, threshold voltage, and mobility have been made on polycide structures with 25-nm gate oxides. These MOS parameters correspond very closely to those obtained for n+ poly-Si gates.