Integrated tapped MOS analogue delay line using switched capacitor technique
Abstract
A tapped MOS analogue delay line based on the switched capacitor technique for realization of low-power analogue LSIs is fabricated using a VLSI process. Excellent characteristics such as large signal handling capability, low total harmonic distortion of -85 dB for 3V(p-p) input and fast operation speed of more than 1 MHz clock rate with negligible charge transfer loss are obtained.
- Publication:
-
Electronics Letters
- Pub Date:
- March 1982
- DOI:
- Bibcode:
- 1982ElL....18..193E
- Keywords:
-
- Analog Circuits;
- Capacitance Switches;
- Delay Lines;
- Large Scale Integration;
- Metal Oxide Semiconductors;
- Signal Processing;
- Adaptive Filters;
- Charge Transfer;
- Fabrication;
- Field Effect Transistors;
- Network Synthesis;
- Signal Distortion;
- Electronics and Electrical Engineering