Research on InGaAs FETs

A process has been established for fabricating In.53Ga.47As JFETs on InP substrates that is capable of making JFETs with small gate lengths (almost equal to 0.5 micrometer), low source resistance (2 omega), low gate series resistance (2 omega), low gate series resistance (< 4 omega), negligible 'sidewall' capacitance, and low gate leakage current (approximately 100 nA). The process involves a shallow localized Zn diffusion and a controlled etch using the gate metal as a mask. The effective gate length is somewhat smaller than the gate metal 'length', thus facilitating the formation of submicron gates. At modest reverse-bias gate voltages, these JFETs have g sub m values approaching twice that which would be expected for corresponding GaAs MESFETs. However, near zero-gate bias, there is substatial g sub m compression, perhaps arising from defects associated with the Zn-diffusion process. Further devise optimization is still required along the lines of increasing channel doping, decreasing gate length, and developing improved diffusion processes (e.g., ion-implantation). Optimized In .53Ga.47As JFETs will probably outperform even the best GaAs MESFETs.