Ion implanted GaAs I. C. process technology
Abstract
This report covers a program on the development of a planar GaAs digital integrated circuit (IC) technology. The main goals of this program were the development and implementation of the fabrication technology, and the demonstration of the feasibility of reaching largescale integration (LSI) with highspeed, lowpower GaAs digital ICs. In approximately 3 1/2 years a planar fabrication process was developed and refined. The program started with the fabrication of the first planar FET transistors using the new process, and the demonstration of Schottky diodeFET logic (SDFL) gates, showing high speed operation of ring oscillators. After this initial stage, many logic circuits have been built. The complexity of these demonstration circuits, involving both combinatorial and sequential logic, grew at a nearly exponential rate. Among the most complex circuits fully demonstrated is a 5 x 5 bit parallel multiplier employing 260 SDFL gates.
 Publication:

Final Technical Report
 Pub Date:
 July 1981
 Bibcode:
 1981ric..reptQ....Z
 Keywords:

 Fabrication;
 Gallium Arsenides;
 Integrated Circuits;
 Ion Implantation;
 Digital Systems;
 Field Effect Transistors;
 Gates (Circuits);
 High Speed;
 Large Scale Integration;
 Logic Circuits;
 Electronics and Electrical Engineering