Viterbi decoder VLSI integrated circuit for bit error correction

A description is presented of the development of a Viterbi decoder VLSI integrated circuit for improved bit error rates of received digital data. The single-chip device provides a 4.3 dB net coding gain at a 0.00001 bit error rate for Quadriphase Shift Keying (QPSK). Attention is given to the encoder, implementation, processing, and the decoder. It is pointed out that a rate 1/2, constraint length 5 Viterbi decoder and convolutional encoder VLSI device have been implemented with 2-micrometer CMOS/SOS technology. The device contains 33,313 transistors within a 201 by 288 mil die size (scribe/scribe) and dissipates less than 100 milliwatts nominal at 5-volt bias.