Semiconductor measurement technology: The design, testing, and analysis of a comprehensive test pattern for measuring CMOS/SOS process performance and control

A Process Validation Wafer (PVW) is a wafer containing only test patterns. One PVW accompanies a product lot during the fabrication process. Test patterns designed to be used on PVWs contain both process parameter test structures and random fault test structures. Eighteen PVWs fabricated in a radiation hardened silicon gate CMOS/SOS process were tested on a high speed computer controlled dc test system. Test results from the process parameter test structures were used to establish the baseline electrical parameters for each product lot and to produce an eight level gray scale wafer map for these parameters.