Testability and reliability of LSI

A number of studies related to testing, testability, and reliability were made and the major results are reported. One study was concerned with the relationship between testing and reliability, which lies in the lack of dependability caused by incomplete testing. An approach to calculating this lack of assurance, based on binary decision diagrams, was formulated and programmed. Initial experience with a first version indicates that care must be exercised in optimizing programming, if large networks are to be handled economically. A major part of the report is concerned with an exhaustive form of the 2n different Walsh coefficients, of which two are particularly useful. The first is just the conventional counting of the number of ones in the response. The second is shown to detect any pin faults, in any combination, with a particularly simple test-equipment implementation that may well serve as a BIT (built-in-test) design. The application of Walsh-coefficient verification to array logic is investigated. Simple PLA's are shown to be readily testable; arrays with flip-flops are also studied and methods for improving their testability are given. The formulation of a testability measure (TM) is described. The TM is calculated on the basis of a gate-level network description. The actual calculations are based on approximations, but their validity can be verified by precise calculations. When the approximations are used, the task of evaluating the testability is much less than finding actual tests.