Test generation using binary decision diagrams

This paper formulates an approach for the development of a test strategy of complex LSI devices using graphical modeling techniques. A simple manual test generation algorithm using binary decision diagrams is presented. The tree-like structure of the binary decision diagram is very similar to that of a controlled di-graph. While the decision diagram describes the logical properties of a device, the controlled di-graph describes information flow through the device. The controlled di-graph is easily derived from the decision diagram. It is also a useful visual aid showing the logical inter-relationship of binary decision diagrams. For the purpose of illustration, a binary decision diagram model and a controlled di-graph model of the 2909 bit sliced microcontroller are presented.