A test pattern generation technique for detection of digital circuits

A new test pattern generation technique is presented that detects 'stuck-at-one' and 'stuck-at-zero' faults in digital circuits using the Boolean equations derived from the circuit schematic. Single output combinational networks are considered for demonstration. The described technique is analogous to Path Sensitization and critical path test generation techniques currently in use. The algorithm is derived for generating input patterns to obtain the maximum fault coverage of a network with the minimum set of input test patterns. Input patterns can be applied to a network under investigation to obtain the output patterns and to determine which faults are not covered by the existing input test patterns. Thus, it can be used as a simulator. For demonstration purposes, all output functions are written as min-terms or sum of products. But the basic technique is applicable to max-terms or product of sums. An example is given using a combination of min-terms and max-terms.