Effect of gate oxide thickness on the radiation hardness of silicon-gate CMOS

Significant improvements have been made in the radiation hardness of silicon-gate CMOS by reducing the gate oxide thickness. The device studied is an 8-bit arithmetic logic unit designed with Sandia's Expanded Linear Array standard cells. Devices with gate oxide thickness of 400, 570 (standard), and 700 A were fabricated. N- and P-channel maximum threshold shifts were reduced by 0.3 and 1.2 volts, respectively, for the thinnest oxide. Approximately, a linear relationship is found for threshold shift versus thickness. The functional radiation hardness of the full integrated circuit was also measured.