Queueing model of a multiprocessor based packet switch for satellite communications
Abstract
The architecture of a multiprocessor based packet switch for satellite communications is presented. The operation of the switch is explained by following a typical packet through the switch. Servicing a packet involves four functions, namely, input, sorting, routing and output functions. A number of microprocessors are assigned to perform each of these functions. A queue theoretic model of the switch is presented. Analytical expressions for the average delay and queue sizes at the various queues and the overall average response time are developed. Graphs showing the effect of a number of design parameters of the switch on its response time and queue sizes are also presented.
- Publication:
-
ICC 1981; International Conference on Communications, Volume 2
- Pub Date:
- 1981
- Bibcode:
- 1981icc.....2...33A
- Keywords:
-
- Airborne/Spaceborne Computers;
- Architecture (Computers);
- Communication Satellites;
- Multiprocessing (Computers);
- Packet Switching;
- Queueing Theory;
- Computer Systems Design;
- Design Analysis;
- Mathematical Models;
- Microprocessors;
- Onboard Data Processing;
- Communications and Radar