An approach to built-in testing on very large-scale integrated/very high-speed integrated circuitry devices

An increase in the amount of circuit elements per chip to numbers in the range from 100,000 to 1,000,000 leads to problems concerning circuit testing. However, the large number of elements per chip makes it also possible to employ a part of the on-chip circuitry for approaches which will ensure system reliability. On-chip self-testing must be part of an overall design strategy that assists in the verification of system operation and the correctness of data. A description is presented of five engineering actions that are useful in providing fault tolerance in systems using very large-scale integrated/very high-speed integrated circuitry devices. These actions are related to the elimination of single-point failures, transient and intermittent error detection and correction, locating self-test and redundant circuitry, the minimization of I/C package lead count, and the utilization of classical reliability concepts.