SDW MOSFET static memory cell

A new SDW (single device well) static memory cell is described. The memory cell, including an access transistor, uses only two SDW MOSFETs, versus four-to-six transistors in conventional static memory cells. Thus, a great saving in silicon area results. Cell static and dynamic performance are discussed and simulated using an appropriate model implemented in the computer-aided circuit analysis program WATAND. The access time of the new cell is comparable to that of conventional MOSFET cells. Using 3 micron technology, a SDW memory cell consumes an area of 600 sq microns and has an average power consumption of 10 microwatts at 5 V supply. Another version of the cell using a polyresistor is also discussed.