SLIC3 - The synchronised/limit cycle conductance controller

The paper presents a detailed laboratory design of a synchronized limit cycle conductance controller (SLIC3), a derivative of the LC3 principle. In the new design, the propagation delay of the detector has been reduced to less than 700 ns by using non-saturating stages, which is necessary to make the detector performance more predictable and compatible with the new power FET technology. In the absence of a synchronized signal, the regulator reverts automatically to LC3 operation, thus maintaining the regulator function although with a loss of the synchronized multiphase low ripple characteristics.