A vertical FET structure for microwave power applications

The realization of a 1 watt power output, silicon, JFET test structure operating at microwave frequencies (1 GHz.) is presented. The N Channel device uses a self-aligned, ion implanted, vertical design that increases the gate packing density and allows high frequency operation. The self-aligned gate was produced by the use of a plasma dry process. An analytical expression for the current voltage characteristics of the device is obtained. This formulation provides an extension to the well-known Shockley theory for field effect transistors for the analysis of structures with small length to width ratios operating under velocity saturation conditions. A transit time formulation is used to obtain values for c sub gs (the gate source small signal capacitance), that together with values of g sub m (the small signal forward mutual conductance) found from the analysis indicated above permits the determination of the elements of a first order equivalent circuit. Finally, a large signal characterization method is employed to obtain operating power R.F. data for the test structure at 1 GHz.