Bipolar structures for BIMOS technologies
Abstract
The purpose of this work is to study the integration of bipolar structures in BIMOS environments. More specifically bipolar structures are studied under the constraints and guidelines of a given MOS technology, e.g., the nonexistence of an n(+) underlayer, and the high epitaxial (substrate) resistivity. A bipolar structure, based on merging a multicollector p-n-p transistor with a multiemitter n-p-n transistor is proposed. The structure takes advantage of the availability of clock signals on a MOS chip, and uses the epitaxial (substrate) resistance as a load. It can be used to realize logic and memory functions.
- Publication:
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IEEE Journal of Solid-State Circuits
- Pub Date:
- April 1980
- DOI:
- Bibcode:
- 1980IJSSC..15..229H
- Keywords:
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- Bipolar Transistors;
- Epitaxy;
- Metal Oxide Semiconductors;
- N-P-N Junctions;
- P-N-P Junctions;
- Technology Utilization;
- Transistor Logic;
- Electrical Resistivity;
- Equivalent Circuits;
- Integrated Circuits;
- Shift Registers;
- Substrates;
- Volt-Ampere Characteristics;
- Electronics and Electrical Engineering