Aspects of integrated circuit reliability

The improvement of integrated circuit reliability is discussed along with methods to determine mean life span. The Masterslice concept is examined, in which standard functions are divided among cells. Complex cellular functions can be implemented with redundancy methods on chips. Error recognition and correction codes in data transfer and storage systems are considered. The single error correction - double error correction code (SEC-DEC) used in storage correction is investigated. Experimental and theoretical models for determining rate of failure are compared. The reliability gain, as represented by the decreasing rate of failure, achieved in the development of storage cells of varying complexity is illustrated.