Practical realization of mod p, p prime multiplier
Abstract
An architecture for implementating mod p, p = (2 to the n-th power) minus (2 to the k-th power) plus 1, p prime multiplier is proposed. Simulated results are presented, and speed metrics based on state-of-the-art memory technology are computed. It is concluded that this multiplier can be used in applications that extend the dynamic range of existing radix-2 type moduli in residue arithmetic units.
- Publication:
-
Electronics Letters
- Pub Date:
- June 1980
- DOI:
- Bibcode:
- 1980ElL....16..466R
- Keywords:
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- Architecture (Computers);
- Digital Simulation;
- Fixed Point Arithmetic;
- Multipliers;
- Adding Circuits;
- Binary Data;
- Computer Components;
- Number Theory;
- Performance Prediction;
- Electronics and Electrical Engineering