Ion implanted GaAs integrated circuit process technology

This report covers the third quarter, Phase 2 of a program on ion implanted planar GaAs integrated circuit technology. The overall objective of this program is the development of a manufacturable process for high-speed low-power GaAs logic circuits. The goal for Phase 1 was to establish the technology, and demonstrate its viability by fabricating circuits reaching MSI complexity. The goal for Phase 2 is to achieve the capability of fabricating GaAs ICs of LSI complexity. The program involves the Rockwell International Electronics Research Center and three subcontractors: Cal Tech, Cornell University and Crystal Specialties, Inc. The most important aspects of the work carried out in this quarter were the gaining of further insight into the causes for conversion of unqualified GaAs substrates, the fabrication of wafers with mask set AR3, and the preparation for evaluating the 3 x 3 parallel multiplier, a new circuit on AR3. This circuit will provide vital information for the design of the more complex circuits, on mask set AR4.