An electrically alterable nonvolatile memory cell using a floating-gate structure

An electrically alterable, floating-gate, nonvolatile memory transistor has been developed, with a cell area of under 500 sq microns, and using an advanced n-channel, polysilicon gate process. Cell programming occurs via hot-electron injection, exhibiting three distinct operating regimes. Erase, on the other hand, is based on field emission from floating gate to control gate. The magnitude of electrical erase is determined by applied bias, device parameters, and processing history, particularly the interlevel oxidation temperature. Analysis of experimental data shows that electrical erase does change programming characteristics significantly, and must be accounted for in circuits design. Memory retention, determined by thermal stress, is comparable to commercially available EPROM's. The memory cell exhibits better than 1000-cycle write/erase capability, with degradation in interlevel conduction being the principal factor limiting endurance.