A fully implanted NMOS, CMOS, bipolar technology for VLSI of analog-digital systems

A fully ion-implanted process allows high-density integration of NMOS, CMOS, and bipolar transistors for VLSI of analog-digital systems. Supply voltage can be 20 V. Thresholds are + or - 1.5 V for p- and n-channel enhancement transistors, respectively. Standard deviation per wafer is 15 mV for the NMOS threshold, while the NMOS gain constant is 30 microamp/sq V. The bipolar transistors have a low-resistance base contact. Current gain beta-F can be set independently. For beta-F 90, the Early voltage is V(A) 110 V. No epi layer, isolation diffusions, or channel stoppers are required. The mask count is 6 for structure definition plus 2 for the masking of implants. The process can be scaled along the learning curve of digital MOS VLSI.