Design automation and testing of diagnosable MOS combinational logic networks

An efficient algorithm for computer-aided synthesis of MOS combinational logic networks is presented. The algorithm synthesizes a completely or an incompletely specified function of a large number of variables. It rapidly generates an easily-testable network with the near-minimum number of complex cells and FET's. The algorithm has been programmed in FORTRAN 4 for UNIVAC 1108 and the results of computer execution are discussed. Statistical data were taken to evaluate the performance of the algorithm and to demonstrate its efficiency. A new testing approach based on a matrix model is used to generate tests for the designed networks.