Design automation and testing of diagnosable MOS combinational logic networks
Abstract
An efficient algorithm for computeraided synthesis of MOS combinational logic networks is presented. The algorithm synthesizes a completely or an incompletely specified function of a large number of variables. It rapidly generates an easilytestable network with the nearminimum number of complex cells and FET's. The algorithm has been programmed in FORTRAN 4 for UNIVAC 1108 and the results of computer execution are discussed. Statistical data were taken to evaluate the performance of the algorithm and to demonstrate its efficiency. A new testing approach based on a matrix model is used to generate tests for the designed networks.
 Publication:

Ph.D. Thesis
 Pub Date:
 May 1978
 Bibcode:
 1978PhDT........25E
 Keywords:

 Computer Aided Design;
 Logic Circuits;
 Metal Oxide Semiconductors;
 Network Synthesis;
 Algorithms;
 Combinatorial Analysis;
 Field Effect Transistors;
 Fortran;
 Matrices (Mathematics);
 Tests;
 Electronics and Electrical Engineering