C-MOS/SIS - Using selective SF6 etching of plane-type 1-102 sapphire
Abstract
A process for selectively etching holes in plane-type 1-102 sapphire using SF6 in H2 is described. SiO2, Si3N4, and combinations thereof are studied as possible etchant masks. Refilling the holes with epitaxial silicon produces an SIS (silicon-in-sapphire) wafer wherein the silicon islands are imbedded into the sapphire substrate. The electrical characteristics of C-MOS/SIS transistors are similar to those of conventionally processed SOS devices.
- Publication:
-
IEEE Transactions on Electron Devices
- Pub Date:
- August 1978
- DOI:
- Bibcode:
- 1978ITED...25..878W
- Keywords:
-
- Cmos;
- Epitaxy;
- Etching;
- Integrated Circuits;
- Silicon Junctions;
- Sulfur Fluorides;
- Masking;
- Production Engineering;
- Sapphire;
- Sos (Semiconductors);
- Substrates;
- Wafers;
- Electronics and Electrical Engineering