Low-noise GaAs FET's prepared by ion implantation

On the basis of ion implantation directly into bulk-grown semi-insulating substrates, low-noise GaAs FETs with a high level of performance have been developed. Substrate selection is simulated by substituting Kr for the implanted dopant species. A layer of reactively sputtered Si3N4 serves as a capping layer preventing surface conversion during post-implantation annealing; Se implants have shown slight redistribution at this stage. Using photolithographic techniques, a gate length of one micron has been selected along with a Ti/Pt/Au gate metal system. A eutectic composition of Au-Ge at 450 C yields low-resistance source and drain ohmic contacts. Device modeling has indicated that an almost ideal active layer profile is obtained by a single-dose Se implant. Devices with a one-micron gate length have shown noise figures of 1.1 dB at 4 GHz with 12 dB associated gain, and 2.1 dB at 10 GHz with 8 dB associated gain. High-frequency measurements with a low-parasitic carrier show a noise figure of 2.5 dB at 15 GHz with 7 dB associated gain.