Thermal resistance of GaAs power FETs
Abstract
A theoretical model has been developed for the calculation of the thermal resistance of the flip-chip packaged parallel-gate FETs. The model utilizes existing transmission line theory and the duality of capacitance and thermal conductance. An infrared scanning microscope (IRSM) has been used for the measurement of the device operating temperature. The computer controlled IRSM using a Barnes infrared microscope provides automatic emissivity calibration and two-dimensional scanning. The resolution of the IRSM is about 35 micrometers. The IRSM has also been used as a diagnostic tool to determine the optimum machine setting for flip-chip bonding. Based on the thermal calculation, FET patterns for various output power levels have been designed for a maximum operating temperature of about 110 C. The measured thermal resistance is in fair agreement with the calculated results.
- Publication:
-
Active Microwave Semiconductor Devices and Circuits
- Pub Date:
- 1977
- Bibcode:
- 1977amsd.proc..297H
- Keywords:
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- Field Effect Transistors;
- Gallium Arsenides;
- Operating Temperature;
- Thermal Resistance;
- Heat Transmission;
- Power Efficiency;
- Temperature Profiles;
- Electronics and Electrical Engineering