Implementation of scramblers for PCM signals with timing-pulse rate

Possibilities for the generation of binary quasi-random sequences by means of multiplexing techniques are discussed. The considered approaches are used as a basis for the implementation of scrambler circuits with low timing-pulse rate and subsequent parallel-series transformation. Procedures for obtaining interleaved sequences from a conventional shift-register generator are considered. A description for obtaining interleaved sequences by means of a series-parallel transformation of the generator structure is also provided, taking into account a method reported by O'Reilly (1975). The basic design of a scrambler in the case of an additive reset scrambler and a multiplicative scrambler is examined and attention is given to the scrambling of PCM signals of high timing-pulse frequency with the aid of an approach involving the use of several parallel channels and subsequent multiplexing.