Computer aided engineering of semi-conductor integrated circuits

The objectives of this program are to remove the empiricism associated with the design and manufacturing of custom integrated circuits for military applications and to reduce the cost of these circuits by devising improved computer-aided engineering techniques. Efforts of research covered by this report are Part I, Semiconductor Device Modeling conducted by the University of Florida and, Part II, Integrated Circuit Process Modeling conducted by Stanford University. Part I of the report deals with: (a) A One-Dimensional Mathematical Model of MOSFET Operation; (b) The Inversion Layer Carrier Mobility in an MOSFET; (c) An Integral Equation-Relaxation Procedure for the Determination of Equilibrium Potentials in Semiconductor Devices; (d) A Test Pattern Model using Monte Carlo Methods of Analysis; (e) Equivalent Circuit Studies; and (f) A Two-Dimensional Model for MOSFET Operation. Part II deals with: (a) Effects of Implantation Damage on Impurity Profiles in Annealed Si and Calculation of Range Profiles and Recoil Implantation in Multi-Layered Media; (b) Thermal Oxidation (a joint effort by Stanford University Integrated Circuits Laboratory, and Fairchild Camera and Instrument Corp. Research and Development Laboratory); (c) Silicon Epitaxy; and (d) A Mathematical Model of Impurity Diffusion (conducted by Louisiana State University).