Procedures for functional partitioning and simulation of large digital systems

Criteria for feasible simulation are developed from considerations of accuracy and efficiency. The popular gate level circuit models are analyzed for the feasibility of simulating them at a functional level. For the feasible models, simulation procedures are developed which permit a stepwise increase in accuracy at little extra overhead. It is also shown that through minor modifications of this procedure, some of the well known problems associated with unknown signals and reconvergent fan outs can be solved. Based on these results, the implementation of a functional simulator is investigated. Two major simulator features are considered, those of partitioning to form functional modules and timing analysis. It is seen that in both cases, the resulting procedures are simple.