High-density CMOS ROM arrays

A single transistor cell and a precharge signal are used to reduce the memory cell area in bulk CMOS ROM arrays to 1.12 sq mil/bit. Use of SOS/CMOS technology further reduces the memory cell area to 0.38 sq mil/bit and makes possible CMOS ROM's of up to 32,768 bits. Operation of both the array and the decoders is controlled by a precharge signal which is generated internally in a way which is transparent to the user. The CMOS ROM's thus produced are competitive with NMOS ROM's in both density and speed, yet retain all of the advantages of static CMOS circuits such as 1-microwatt power dissipation, full 2.8-15 V voltage operating range, and full -55 C-125 C temperature range.