High-reliability, low-cost integrated circuits

Wafer fabrication for sample generation has been completed on all integrated-circuit types. The critical experiments completed to data have resulted in the unification of the COSMOS and bipolar metallization processes, optimization of the gold-interconnect thickness, development of a suitable COSMOS silicon nitride-silicon oxide gate dielectric, and optimization of the gold bond-pad height. The platinum layer thicknesses required for an effective diffusion barrier and platinum silicide formation have been determined. Preliminary reliability testing has been initiated and data generated on a 250 C bias-life test. A failure mechanism associated with high temperature life tests and epoxy molding compounds has been identified; packaging techniques designed to eliminate this failure mode are being investigated. A preliminary cost baseline has been established.