A master slice design concept based on master cells in ESFI-SOS-CMOS technology
Abstract
The ESFI-SOS system (epitaxial silicon films on insulators-silicon on sapphire) offers advantages over conventional bipolar microprocessor technology due to the system's higher packing density and smaller quiescent power dissipation, while retaining a comparable switching speed. This paper discusses the design and operation of a master cell structure adapted to ESFI-SOS technology. The choice of cell structure is based on maximum complimentarity of cell components. The transistor dimensions are chosen on the basis of a compromise between maximum switching speed and maximum packing density. A description of a dual D-type master-slave flipflop is presented, outlining the interrelationship between control circuits and other system components.
- Publication:
-
Siemens Forschungs und Entwicklungsberichte
- Pub Date:
- 1976
- Bibcode:
- 1976SiFoE...5..344G
- Keywords:
-
- Chips (Electronics);
- Cmos;
- Flip-Flops;
- Large Scale Integration;
- Silicon Films;
- Sos (Semiconductors);
- Bipolar Transistors;
- Epitaxy;
- Insulators;
- Logic Circuits;
- Multiplexing;
- Electronics and Electrical Engineering