A CCD memory chip for radar image processing
Abstract
Considerations for the design of a digital Charge Coupled Devices (CCD) memory will be discussed. Starting from commercial CCD, the design characteristics of a second generation CCD will be derived. The economically feasible capacity and its dependency on the technology lead to the definition of performance parameters and the chip organization. A Serial-Parallel-Serial (SPS) organization will be found most suitable and design considerations of SPS blocks will be discussed. Finally, the overall design of a 32 kbit CCD will be described.
- Publication:
-
NASA STI/Recon Technical Report N
- Pub Date:
- 1976
- Bibcode:
- 1976STIN...7823302R
- Keywords:
-
- Charge Coupled Devices;
- Chips (Memory Devices);
- Image Processing;
- Radar Imagery;
- Surveillance Radar;
- Computer Storage Devices;
- Moving Target Indicators;
- Shift Registers;
- Communications and Radar