A companded delta modulator with low power consumption

A companded delta modulator for coding speech signals is described. The circuit is designed for low power consumption, and is primarily intended for operation at 16 kilobits per second. The principles of operation are described, and full circuit details are included. An appendix gives the complete test procedure used to check whether the equipment is operating correctly. Results of electrical measurements of performance are presented, but not intelligibility or other subjective test results. The equipment was used in experimental models of a military subset and also for subjective assessment purposes.