Radiation hardened p-surface channel CCD's

A process for total dose hardening of surface p-channel CCD's with overlapping polysilicon gates has been developed by optimizing the process steps associated with the gate oxides and polysilicon gates. 16-bit shift registers fabricated with this process can be operated up to 1 Mrad (Si) with threshold voltage shifts not above 2V for the buried gates, and not above 1.5V for the surface gates on the best devices fabricated. The charge transfer efficiency for the devices with -10V gate bias during irradiation is unchanged after 1 Mrad (Si), but drops to 0.999 for the devices with 0V gate bias during irradiation. The average dark current increases to only 1.75 times the initial value after 1 Mrad (Si) for devices with -10V gate bias during irradiation, and to 4 times the initial value for the devices with 0V gate bias. No additional dark current spikes are observed up to 1 Mrad (Si).