Total-dose radiation-hardened COS/MOS integrated circuits

The work on radiation-hardened COS/MOS integrated circuits described in this report was done in two phases. Under Phase I, work was done to evaluate the effects of various SiO2 channel-oxidation techniques on the radiation susceptibility of bulk-silicon and SOS COS/MOS circuits. Procedures for ion-implanting of aluminum in channel oxide and for evaluating characteristics that could be used to predict the radiation hardness of processed wafers were performed. Under Phase II, emphasis has been placed on developing techniques for improving the radiation hardness of COS/MOS circuits on sapphire substrates, and radiation-hardened COS/MOS-on-bulk-silicon integrated circuits were produced. Summaries of the various experimental processes are included.