Static ESFI MOS /SOS/ cells for high-density memories
Abstract
Approaches for reducing the memory cell area by modifying the cell layout are shown. A five-transistor cell is considered along with a two-transistor cell with two branches and a two-transistor cell with one branch. An investigation is conducted concerning the behavior of word and bit lines on an insulator. The indicated circuit design methods make it possible to increase the density of static MOS memory cells without a reduction in the line dimensions. It is feasible to obtain with static ESFI MOS memory cells the density level provided by dynamic MOS memory cells.
- Publication:
-
Siemens Forschungs und Entwicklungsberichte
- Pub Date:
- 1975
- Bibcode:
- 1975SiFoE...4..220G
- Keywords:
-
- Computer Storage Devices;
- Metal Oxide Semiconductors;
- Network Synthesis;
- Silicon Films;
- Transistor Circuits;
- Epitaxy;
- Fabrication;
- Field Effect Transistors;
- Gates (Circuits);
- Integrated Circuits;
- Miniature Electronic Equipment;
- Thin Films;
- Volt-Ampere Characteristics;
- Electronics and Electrical Engineering