Advanced integrated-circuit technology for micropower ICs. Integrated circuits

A four-mask epitaxial v-groove (EVG) bipolar IC fabrication process uses a nonuniform N/N(-)/i layer and anisotropic etching of 1-0-0 silicon to eliminate conventional buried layer and isolation diffusions and to permit the use of an unmasked base diffusion. A five-mask EVG process permits fabrication of lateral pnp devices. The EVG structure offers simpler processing, smaller isolation capacitors, lower parasitic collector resistances, and larger packing densities than conventional processing. Reduced isolation capacitance provides good micropower performance. Process details are described. An epitaxial v-groove n-channel MOS (VMOS) logic structure suitable for 5-volt high-speed random logic was fabricated.