Blocking gate added logic for enhancing testability in LSI circuits

A blocking gate added logic technique for enhancing the test generation and selection for large scale integrated circuits was developed. The blocking gates and one input pin are added to the original circuit in such a way that if the extra input pin is in the 0 state, the circuit operates in normal mode and the added logic has no effect on its operation. When the extra input pin is in the 1 state, the circuit is in test mode and the blocking gates which were inserted in a few key points in the circuit block the propagation of some logical values while enabling the propagation of others. When the blocking gates are used to improve detectability, the circuit is modelled as a collection of input neighborhoods (IND) where each IND consists of a memory element or primary output, together with the combinational network which feeds it. Several algorithms for blocking gate insertion are tried and compared by using a testability measure.