An experimental multiplier circuit based on superconducting Josephson devices
Abstract
This paper describes the design, testing, and operation of a 4-bit multiplier circuit based on Josephson tunneling logic (JTL) gates. The algorithm adopted was that of a simple serial 4-bit multiplier consisting of a 4-bit adder with ripple carry, together with a four phase, 8-bit accumulator shift register. The circuit, fabricated using a 25-micron minimum linewidth technology, operated with a minimum cycle time of 6.67 ns giving a 4-bit multiplication time of 27 ns with an average power dissipation of 35 microwatts per logic gate. With better external pulse generators, or internal Josephson junction generators, the present circuit has been simulated to operate with a 3.0-ns cycle giving a 4-bit multiplication time of 12 ns.
- Publication:
-
IEEE Journal of Solid-State Circuits
- Pub Date:
- October 1975
- DOI:
- 10.1109/JSSC.1975.1050624
- Bibcode:
- 1975IJSSC..10..360H
- Keywords:
-
- Digital Systems;
- Josephson Junctions;
- Logic Circuits;
- Multipliers;
- Network Synthesis;
- Superconductors;
- Adding Circuits;
- Algorithms;
- Electron Tunneling;
- Gates (Circuits);
- Logic Design;
- Shift Registers;
- Electronics and Electrical Engineering