Effects of redundancy on fault detection and diagnosis in combinational logic circuits

The effect of undetectable faults on fault detection and diagnosis is studied. Methods such as judicious selection of a test set and use of additional circuit imputs are formulated for minimizing any adverse effects of redundancy. A computer program is developed which will simulate any combinational logic circuit for the purpose of logic verification and to determine fault detectibility. Second generation faults are calculated by a subroutine called upon by the program if any redundancy is discovered in the circuits.