An efficient algorithm of generating fault detection and location test sets for combinational logic circuits
An efficient algorithm is presented to generate a fault detection test set for detecting every detectable single fault and a fault location test set for locating every single fault to its indistinguishable class in an arbitrary combinational logic circuit. The same method can be applied to both redundant and irredundant circuits. The order of the application of the generated tests to the circuit is immaterial. The detection test set provided remains valid no matter what undetectable stuck-at faults occur in the circuit. Optimum detection test set and optimum location test set are efficiently obtained from the detection test set and the location test set respectively. The algorithm utilizes the properties of the structure and parity-observing-output-functions (SPOOF's) of the given combinational logic circuit.
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- Error Detection Codes;
- Logic Circuits;
- Computer Programming;
- Quality Control;
- Electronics and Electrical Engineering