Contour deposition—A new epitaxial deposition technique for semiconductor devices and integrated circuits
One limitation of the use of epitaxial deposition in semiconductor device integrated circuit design and construction has been the unsuitability of the process to produce regions with well defined doping and accurately controlled geometry in a crystal with a flat surface. A new process called "Contour Deposition" overcomes this limitation. This process exploits the observed phenomenon that epitaxial deposition of silicon tends to follow the contour of the substrate surface. A depression etched into a semiconductor substrate before epitaxy is filled during the subsequent deposition. If the crystal is polished subsequently, the structure obtained has a flat surface and an epitaxially deposited region. With sufficient attention given to polishing techniques the process was found very reproducible and epitaxial pockets up to 20 μ deep were produced with a tolerance of ±1 μ on the depths over the whole are of the silicon slice. An application of the technique is to widen the range of devices that could be built into a semiconductor crystal with compatible techniques, MOS transistor devices with junction transistors, n-p-n, p-n-p transistor pairs, complementary pair MOS transistors. The technique can also be used to produce isolated regions in a semiconductor integrated circuit with low parasitic capacitance because of the favourable geometry and doping of the isolation p-n junction. Highly conducting layers can be buried either by diffusion prior to epitaxy, or formed during epitaxy to reduce series resistance.